IEEE VLSI PROJECTS

 IEEE VLSI PROJECTS

 

IEEE VLSI PROJECTS

• 32-bit RISC CPU Based on MIPS
• A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
• A Spurious-Power Suppression Technique for Multimedia/DSP Applications
• A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique (2010)
• An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform
• An Efficient Architecture for 3-D Discrete Wavelet Transform
• DDR3 based lookup circuit for high-performance network processing
• Design and Implementation of 10/100 Mbps (Mega bits per second) Ethernet Switch for Network applications (2010)
• Design and Implementation of Digital low power base band processor for RFID Tags (2010)
• Design and Implementation of Efficient Systolic Array Architecture for DWT (Discrete Wavelet Transform) (2010)
• Design and Implementation of High Speed DDR SDRAM (Dual Data Rate Synchronously Dynamic RAM) Controller (2010)
• Design and Implementation of Lossless DWT/IDWT for Medical Images
• Design and Implementation of OFDM Transmitter (VHDL)
• Design and Implementation of Reversible Watermarking for JPEG2000 Standard
• Design and Implementation of USB 2.0 Transceiver Macro-cell Interface (UTMI) (2010)
• Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm
• Design of 16-bit QAM (Quadrature Amplitude Modulation) Modulator
• Design of 16-bit QPSK (Quadrature Phase Shift Keying)
• Design of 8-bit Microcontroller (VHDL)
• Design of 8-Bit Pico Processor (VHDL)
• Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix.
• Design of AES (Advanced Encryption Standard) Encryption Algorithm with 128- bits Key Length
• Design of AES (Advanced Encryption Standard) Encryption and Decryption Algorithm with 128-bits Key Length
• Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block


• Design of an ATM (Automated Teller Machine) Controller
• Design of an Bus Bridge between OCP and AHB Protocol (2010)
• Design of CRC (Cyclic Redundancy Check) Generator (Verilog)
• Design of Data Encryption Standard (DES)
• Design of Digital FM Receiver using PLL (Phase Locked Loop)
• Design of Distributed Arithmetic FIR Filter
• Design of Dual Elevator Controller
• Design of Gigabit Ethernet MAC (Medium Access Control) Transmitter
• Design of JPEG Image compression standard
• Design of On-Chip Bus with OCP Interface
• Design of RS-232 System Controller
• Design of Triple Data Encryption Standard (DES)
• Design of Universal Asynchronous Receiver Transmitter (UART)
• Efficient FPGA implementation of convolution
• FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging
• High Performance Complex Number Multiplier Using Booth-Wallace Algorithm
• High Speed Hardware Implementation of 1D DCT/IDCT
• High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming
• High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures
• Implementation of a visible Watermarking in a secure still digital Camera using VLSI design
• Implementation of FFT/IFFT Blocks for OFDM
• Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms
• Multiplication Acceleration Through Twin Precision
• Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
• The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation

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